PCD
?
T2_DISABLED, T2_DIV_BY_1, T2_DIV_BY_4, T2_DIV_BY_16
period is a int 0-255 that determines when the clock value is reset,
postscale is a number 1-16 that determines how many timer overflows before an
interrupt: (1 means once, 2 means twice, and so on).
Returns:
Function:
Availability:
Requires:
Examples:
undefined
Initializes timer 2. The mode specifies the clock divisor (from the oscillator clock).
The timer value may be read and written to using GET_TIMER2() and
SET_TIMER2(). Timer 2 is a 8 bit counter/timer.
This function is only available on devices with timer 2 hardware.
Constants are defined in the devices .h file.
setup_timer_2 ( T2_DIV_BY_4, 0xc0, 2);
// At 20mhz, the timer will increment every 800ns,
// will overflow every 154.4us,
// and will interrupt every 308.8us.
Example
Files:
Also See:
get_timer2(), set_timer2(), Timer2 Overview
setup_timer_3( )
Syntax:
setup_timer_3 ( mode )
Parameters: Mode may be one of the following constants from each group or'ed (via |)
together:
?
T3_DISABLED, T3_INTERNAL, T3_EXTERNAL,
T3_EXTERNAL_SYNC
?
T3_DIV_BY_1, T3_DIV_BY_2, T3_DIV_BY_4, T3_DIV_BY_8
Returns:
Function:
Availability:
Requires:
280
undefined
Initializes timer 3 or 4.The mode specifies the clock divisor (from the oscillator
clock). The timer value may be read and written to using GET_TIMER3() and
SET_TIMER3(). Timer 3 is a 16 bit counter/timer.
This function is only available on devices with timer 3 hardware.
Constants are defined in the devices .h file.
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